1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular to a semiconductor memory device of FIFO (First In First Out) type to be used for picture recording or the like.
2. Description of the Related Art
A field memory or a frame memory adapted for recording graphic data or image data is normally composed of a semiconductor memory device of FIFO type. Since it processes image data, the semiconductor memory device of the FIFO type is required to operate at high speed and to have a sufficiently large memory capacity. In order to meet these requirements, a semiconductor memory device provided with a memory cell array is usually employed. The memory cell array is constructed by using a dynamic memory cell which can be highly integrated. The memory device also has respective registers for reading and writing connected to each pair of bit lines of the memory cell array.
FIG. 1 shows the structure of a memory cell portion and a data register portion of the semiconductor memory device of the conventional FIFO type. In the memory device, memory cell array 1 of universally known structure is composed of memory cells C.sub.11 to C.sub.mn of a dynamic type arranged in the of a matrix of m rows and n columns.
In memory cell array 1, there are provided word lines WL.sub.1 to WL.sub.m for selection of rows and bit line pairs D.sub.1 /D.sub.1 to D.sub.n /D.sub.n for reading or writing data from or into the memory cells. The memory cell array 1 is arranged so that the data held in the memory cells selected by the word line is transmitted from the memory cells to bit lines D.sub.1 to D.sub.n and D.sub.1 to D.sub.n.
Each of bit line pairs D.sub.1 /D.sub.n to D.sub.n /D.sub.n is provided with a balancer 2 and a sense of amplifier 3. The balancer 2 receives balance signal BL and reference voltage Ref and precharges the corresponding bit line pair to reference voltage Ref according to balance signal BL. The sense amplifier 3 is a differential amplifier and is activated by two sense amplifier activation signals SEP, SEN to amplify the data transmitted to the bit line pair. Each of the bit line pairs D.sub.1 /D.sub.1 to D.sub.n /D.sub.n is provided with a read data register RR.sub.1 to RR.sub.n an a write data register WR.sub.1 to WR.sub.n.
Further, the semiconductor memory device comprises a read register switch 5, a read register pointer 6, a write register switch 10 and a write register pointer 11. The read register switch 5 is composed of 2n transfer gates RDT.sub.a to RDT.sub.z. These transfer gates connect each bit line pair D.sub.1 /D.sub.1 to D.sub.n /D.sub.n and each read data register RR.sub.1 to RR.sub.n corresponding to the read transfer signal RDTG inputted to all of the transfer gates. For example, transfer gate RDT.sub.a connects bit line D.sub.1 and one end of read data register RR.sub.1, and transfer gate RDT.sub.b connects bit line D.sub.1 and the other end of read data register RR.sub.1.
The read register pointer 6 consists of an n-stage shift register 7 for read and a number n of transfer gates PR.sub.1 to PR.sub.n. Transfer gates PR.sub.1 to PR.sub.n are each used to connect one of the read data registers RR.sub.1 through RR.sub.n to the read data bus RB corresponding to the output of the shift register 7. For example, transfer gate PR.sub.1 is controlled by the output of the first stage of shift register 7 to connect one end of read data register RR.sub.1 and read data bus RB, and transfer gate PR.sub.2 is controlled by the output of the second stage of shift register 7 to connect read data register RR.sub.2 and read data bus RB. The shift register 7 for read is arranged so as to operate in synchronization with the read clock RCK.
The write register switch 10 is composed of a number 2n of transfer gates WDT.sub.a to WDT.sub.z. These transfer gates each connect each of bit line pairs D.sub.1 /D.sub.1 to D.sub.n /D.sub.n and each write data register WR.sub.1 to WR.sub.n corresponding to the write transfer signal WDTG inputted to all of the transfer gates. For example, transfer gate WDT.sub.a connects bit line D.sub.1 and one end of write data register WR.sub.1, and transfer gate WDT.sub.b connects bit line D.sub.1 and the other end of write data register WR.sub.1.
The write register pointer 11 consists of an n-stage shift register 12 for write and n pairs of transfer gates PW.sub.1 to PW.sub.n. Transfer gates PW.sub.1 to PW.sub.n are each used to connect one of the write data registers WR.sub.1 through WR.sub.n to the write data bus WB/WB corresponding to the output of the write shift register 11. The write data bus WB/WB is composed of a pair of write data lines WB, WB. For example, transfer gate PW.sub.1 is controlled by the output of a first stage of shift register 11 to connect one end of write data register WR.sub.1 and write data line WB and to also connect the other end of write data register WR.sub.1 and write data line WB. The shift register 11 for write is made so as to operate in synchronization with the write clock WCK.
In the semiconductor memory device, data is inputted from outside the device to write data registers WR.sub.1 to WR.sub.n synchronized with the write clock WCK through write data bus WB/WB. In this case, the data is inputted into the write data register selected by the write register pointer 11. On the one hand, data is read from read data registers RR.sub.1 to RR.sub.n to outside the device in synchronization with the read clock RCK. The data of the read data register selected by the read register pointer 6 is transmitted to the read data bus RB.
Next will be described the data transfer operation for writing. FIG. 2A is a timing chart illustrating the data transfer operation from the write data register to the memory cell. The following description will focus on the operation of bit line pair D.sub.1 /D.sub.1 to be executed when word line WL.sub.1 is selected. It is assumed that high-level data is stored in memory cell C.sub.11, and data in reverse phase to this high-level data is stored in write data register WR.sub.1.
Balance signal BL is first changed to a low level, and precharging of bit lines D.sub.1 to D.sub.n and D.sub.1 to D.sub.n is then halted to put these bit lines in a floating state. Next, word line WL.sub.1 is turned to the high level. At this time, data stored in memory cell C.sub.11 is transmitted as a minute difference voltage between bit lines D.sub.1 and D.sub.1. However, by making write transfer signal WDTG shift to the high level for some fixed time, signals with the phase reverse to that of the data of memory cell C.sub.11 will be transmitted from write data register WR.sub.1 to bit line pair D.sub.1 /D.sub.1. Consequently, the data of write data register WR.sub.1 is inputted into the sense amplifier 3 as a difference voltage between bit lines D.sub.1 and D.sub.1. Thereafter, by making the sense amplifier activation signals SEP, SEN transit from reference voltage level Ref to the power source level and to the ground level, respectively, the electric potentials of bit lines D.sub.1 , D.sub.1 are amplified to the ground and power source potential levels, respectively and transmitted to memory cell C.sub.11.
By changing word line WL.sub.1 to the low level to finish the writing of data into memory cell C.sub.11, and by concurrently changing balance signal BL to the high level to restart the precharging of each bit line, a series of the writing operation is completed. Although this description has been made with reference to memory cell C.sub.11, memory cells C.sub.12 to C.sub.1n are also connected to word line WL.sub.1, and data are also stored in memory cells C.sub.12 to C.sub.1n together with the storage of the data in memory cell C.sub.11. The data to be stored in memory cells C.sub.12 to C.sub.1n is the same as the data stored in each of write data registers WR.sub.2 to WR.sub.n.
Next will be described the data transfer operation for reading. FIG. 2B is a timing chart illustrating the data transfer operation from a memory cell to a read data register.
Balance signal BL is first changed to the low level, and precharging of bit lines D.sub.1 to D.sub.n and D.sub.1 to D.sub.n is then stopped to put these bit lines into a floating state. Word line WL.sub.1 is then changed to the high level. As a result, the data held in memory cell C.sub.11 is transmitted as a minute difference voltage between bit lines D.sub.1 and D.sub.1 and inputted into the sense amplifier 3. By making sense amplifier activation signals SEP, SEN transit from the reference voltage level to the power source and ground levels, respectively, the electric potentials of bit lines D.sub.1, D.sub.1 are amplified to the power source and ground levels, respectively. At this time, by making the read transfer signal RDTG shift to the high level for some fixed time, the data amplified by sense amplifier 3 is read out to read data register RR.sub.1, and concurrently, this amplified data is transmitted again to memory cell C.sub.11. By changing word line WL.sub.1 to the low level, data reading from memory cell C.sub.11 is finished. Since word line WL.sub.1 is connected to memory cells C.sub.12 to C.sub.1n, the data is also refreshed in each of these memory cells C.sub.12 to C.sub.1n. Next, by changing balance signal BL to the high level to restart the precharging of each bit line D.sub.1 to D.sub.n and D.sub.1 to D.sub.n, a series of reading operations is completed.
In FIFO type semiconductor memory devices with a basic structure of this type, it is not possible to directly designate an estimated address from outside in order to select a particular memory cell, so that when defects are detected or troubles are generated while developing a memory device itself or after it is assembled into a user's device, it is difficult to analyze the cause of the defects or troubles. Therefore, in many cases, a test circuit is provided in the memory device for easy analysis of defects and shortening the analysis time. For analysis of defects, it is important to discover whether the cause of the defects is in the memory cell or in the data register, it is consequently indispensable to provide as a function of the test circuit a bypass transfer function for direct transfer of data from a write data register to a read data register without passing through the memory cell.
The operation of transferring data from a write data register to a read data register will be described with reference to the semiconductor memory device shown in FIG. 1. FIG. 3 is a timing chart illustrating the bypass transfer operation of this semiconductor memory device. This bypass transfer operation corresponds to the read and write operation to be performed in succession.
Balance signal BL is first changed to the low level, and balancing and precharging of bit lines D.sub.1 to D.sub.n and D.sub.1 to D.sub.n are then stopped. Word line WL.sub.1 is then turned to the high level, at which time, data stored in memory cell C.sub.11 is transmitted as a minute difference voltage between bit lines D.sub.1 and D.sub.1. Here, by shifting write transfer signal WDTG to the high level for some fixed time, the data stored in write data register WR.sub.1 is inputted into bit lines D.sub.1, D.sub.1. In an example shown in FIG. 3, the data stored in write data register WR.sub.1 is of a phase that is the reverse of that of the data stored in memory cell C.sub.11.
As a result, the data of write data register WR.sub.1 is inputted into the sense amplifier 3 connected to bit line pair D.sub.1 /D.sub.1 as a voltage difference between bit lines D.sub.1 and D.sub.1. Subsequently, by making sense amplifier activation signals SEP and SEN transit from the reference voltage level to the power source level and ground level, respectively, the electric potentials of bit lines D.sub.1, D.sub.1 are amplified to the ground and power source voltage levels, respectively. At this time, read transfer signal RDTG is maintained at the high level for a certain fixed time, and consequently, the amplified data is read on read data register RR.sub.1.
The data thus read out is identical to the data stored in write data register WR.sub.1. Next, by changing word line WL.sub.1 to the low level and balance signal BL to the high level and successively starting the balancing and precharging of bit lines D.sub.1 to D.sub.n and D.sub.1 to D.sub.n, a series of bypass transfer operations is completed.
By the above operations, once the data of write data registers WR.sub.1 to WR.sub.n has been transmitted to bit lines, it is amplified by the sense amplifier 3 and then transmitted as amplified data to read data registers RR.sub.1 to RR.sub.n, respectively. Therefore, when some irregularity in memory cell array 1 causes an abnormal voltage of the bit lines, the normal bypass transfer operation is disturbed, and as a result, it is difficult to clearly distinguish irregularities in the memory cell side from irregularities in the data register side. The conventional FIFO type semiconductor memory device described above is therefore problematic in that it does not allow an easy analysis of irregularities.